Field of the Invention
The present invention relates generally to microchips, microchip packaging, and the interconnection of microchips.
Description of Related Art
Affordable electronic systems having increased functionality and smaller packaging have been in demand for many years. Significant advances in microchip packaging and system design, including Quilt Packaging of microchips, have resulted from such demand. The process of forming interconnect nodules on the surface, or protruding laterally from the surface, of microchips is known generally in the art. One example of such technology is illustrated by U.S. Pat. No. 7,612,443, which is incorporated herein by reference.
As microchips are being formed, etching, metal plating, photolithography and other processes allow for the formation of solid metal contacts (nodules) along the vertical edges of microchips. In an example of forming microchips that include interconnect nodules, also called Quilt Package or QP nodules herein, semiconductor wafers contain multiple microchips with each microchip separated from its neighboring microchips on the wafer by “streets.” Trenches are etched in the street regions and are passivated by forming one or more layers on the exposed surfaces of the trenches using techniques known in the art. Passivation techniques can include PECVD nitride, PECVD oxide, sputtered oxide, and low-k dielectrics or other dielectric materials. A resist coating is then applied to the wafer and subsequently removed from the trenches to form openings in the resist coating over the trenches. Metal is deposited into trenches through the openings in the resist. After the resist is removed, a plating process then is applied to the metal to form metal interconnect or QP nodules. The interconnect or QP nodules are further processed, including a chemical-mechanical polishing step, the addition of dielectric material, and the formation of on-chip electrical connections. Interconnect or QP nodules can also be formed to protrude over the edge of the microchip by performing an anisotropic etch followed by an isotropic etch causing vertical surfaces of the wafer to recede, allowing the interconnect or QP nodules to protrude beyond the edges of the microchip. For additional details regarding forming interconnect or QP nodules, see U.S. Pat. No. 7,612,443.
Wafer processing using these known techniques allows microchips to be manufactured and placed side by side with electrical interconnection directly through the interconnect or QP nodules without having to go through first level packaging to printed circuit boards or multi-chip modules. This process of directly connecting chips to form a quilt-like pattern is known in the art as Quilt Packaging. Nodules that protrude over the edge of the microchip (also known as edge interconnection nodules or Quilt Package (QP) nodules) further allow for increased integration of system components without sacrificing performance or increasing cost. It is desirable to use Quilt Packaging in ways not disclosed in the prior art to further increase these benefits.